ARM coprocessor CP15 Summary

Introduction
* CP15 is a coprocessor of ARM chip, it used to configure and control the ARM core modules - The caches, Tightly-Coupled Memories (TCMs), Memory Management Unit (MMU), and most other system options.

Instructions
* You can only access CP15 registers with MRC and MCR instructions in a privileged mode.

mcr{cond} p15, <Opcode_1>, <Rd>, <CRn>, <CRm>, <Opcode_2>
mrc{cond} p15, <Opcode_1>, <Rd>, <CRn>, <CRm>, <Opcode_2>

- The Opcode_1 and Opcode_2 field Should Be Zero except when the values specified are used to select the desired operations.
- The CRm field should be c0 except when the the register specified are used to select the desired behavior.

Registers
* c0~c15
- c0: used to read ID code/Cache type/TCM status
> read ID code:

mrc p15, 0, <Rd>, c0, c0, 0

> read Cache type:

mrc p15, 0, <Rd>, c0, c0, 1

> read TCM status:

mrc p15, 0, <Rd>, c0, c0, 2

- c1: used to enable/disable caches and MMU
> read control register:

mrc p15, 0, <Rd>, c1, c0, 0

> write control register:

mcr p15, 0, <Rd>, c1, c0, 0

- c2: r/w Translation Table Base (TTB)

mrc p15, 0, <Rd>, c2, c0, 0; read TTBR
mcr p15, 0, <Rd>, c2, c0, 0; write TTBR

- c3: Domain access control

mrc p15, 0, <Rd>, c3, c0, 0; read domain access permissions
mcr p15, 0, <Rd>, c3, c0, 0; write domain access permissions

- c4: Reserved in ARM926EJ-S
- c5: Data fault status/Instruction fault status
- c6: Fault address
- c7: Cache operations

mrc p15, 0, <Rd>, c7, c7, 0; Invalidate ICache and DCache
mcr p15, 0, <Rd>, c7, c5, 0; Invalidate ICache
mcr p15, 0, <Rd>, c7, c5, 1; Invalidate ICache single entry (MVA)
mcr p15, 0, <Rd>, c7, c5, 2; Invalidate ICache single entry (Set/Way)
mcr p15, 0, <Rd>, c7, c13, 1; Prefetch ICache line (MVA)
mcr p15, 0, <Rd>, c7, c6, 0; Invalidate DCache
mcr p15, 0, <Rd>, c7, c6, 1; Invalidate DCache single entry (MVA)
mcr p15, 0, <Rd>, c7, c6, 2; Invalidate DCache single entry (Set/Way)
mcr p15, 0, <Rd>, c7, c10, 1; Clean DCache single entry (MVA)
mcr p15, 0, <Rd>, c7, c10, 2; Clean DCache single entry (Set/Way)
mrc p15, 0, <Rd>, c7, c10, 3; Test and clean DCache
mcr p15, 0, <Rd>, c7, c14, 1; Clean and invalidate DCache entry (MVA)
mcr p15, 0, <Rd>, c7, c14, 2; Clean and invaliate DCache entry (Set/Way)
mrc p15, 0, <Rd>, c7, c14, 3; Test, clean, and invalidate DCache
mcr p15, 0, <Rd>, c7, c10, 4; Drain write buffer
mcr p15, 0, <Rd>, c7, c0, 4; Wait for interrupt

> Clean the entire DCache:

tc_loop:
mrc p15, 0, r15, c7, c10, 3; test and clean, pc is not changed by this instrunction
bne tc_loop

> Clean and invalidate the entire DCache:

tci_loop:
mrc p15, 0, r15, c7, c14, 3; test clean and invalidate
bne tci_loop

- c8: (W) TLB operations
- c9: Cache lockdown/TCM region

mrc p15, 0, <Rd>, c9, c0, 0; read DCache lockdown register
mcr p15, 0, <Rd>, c9, c0, 0; write DCache lockdown register
mrc p15, 0, <Rd>, c9, c0, 1; read ICache lockdown register
mcr p15, 0, <Rd>, c9, c0, 1; write ICache lockdown register

- c10: TLB lockdown
- c11/c12: Reserved in ARM926EJ-S
- c13: FCSE PID/Context ID
- c14: Reserved in ARM926EJ-S
- c15: Test configuration